1. Field Of The Invention
This invention relates to computer systems, and more particularly, to a method and apparatus for providing flow control of input/output operations in computer systems.
2. History Of The Prior Art
Modern computer system are typically based on an architecture which was first offered in the Digital Equipment Corporation (DEC) PDP 11 computer. One problem with this architecture as with earlier IBM and CDC mainframe architectures is that writing directly to the input/output devices of the system by an application program is prohibited. Although this architecture allows all of the facilities of the central processing unit to be used for input/output, it requires that the operating system running on the central processing unit attend to all of the input/output functions using trusted code. This significantly slows any input/output operation of the computer.
In contrast to earlier mainframe systems, in this architecture, there is no process by which the input/output performance of the system can be increased except by increasing the speed of the central processing unit or the input/output bus. This is an especial problem for programs which make heavy use of input output/devices such as video and game programs which manipulate graphics and high quality sound extensively.
In a modern computer, the central processing unit and the input/output devices operate at different speeds. It can be very inefficient for a modern central processing unit to wait until an input/output write operation is complete before performing the next operation which often has nothing to do with input/output. On the other hand, a central processing unit has to wait for the result of a read operation because it needs the result produced.
Since most central processing unit accesses to input/output devices are write operations, the designers of systems and input/output devices attempt to decouple the central processing unit and input/output devices as far as write operations are concerned by implementing write queues using first-in first-out (FIFO) write buffers. These buffers may appear at various places in a particular implementation: as a part of the central processing unit, as part of a bridge chip, or as part of an input/output device.
One problem raised in systems using FIFO buffers is that an input/output device and the buffers supplying it must accept all information written to them over the input/output bus. Although some input/output buses allow devices to "hold off" writes, that is, delay the completion of the write operation until the device has enough resources available to store the data, there is always a limit to how long a write can be held off. If a write is held off too long the data will be lost. In the limit, the input/output device has no alternative but to store all data written to it. In a system utilizing FIFO buffers for storage of this data at the input/output device, the FIFO buffers must ultimately store the data.
Since any practical input/output device will have limited FIFO buffer storage for holding data written to it over the input/output bus, any architecture for input/output devices must include some technique for controlling the flow of data so that this storage is not exhausted.
It is desirable to provide a means for providing flow control for a computer system or similar system utilizing FIFO buffers to receive data so that the operation may proceed as rapidly as possible without loss of data. A new input/output architecture which allows input/output operations to proceed at a faster rate by allowing application programs to write directly to input/output devices used with advanced multi-tasking operating systems has now been designed. One of the features of this system is the use of a write buffering arrangement including FIFO buffers. These FIFO buffers include flow control circuitry including registers which store a value indicating the amount of free space remaining in the FIFO buffer. By ascertaining this amount before data is transferred to a FIFO buffers and sending no more than that amount, no data is lost and transmission speed is maintained. However, such a system requires that the value indicating the amount of space available in a FIFO buffer be transferred to the system processor continuously during operation of the system. This places a substantial overhead on the operation of the system.
In many situations the FIFO buffers are able to transfer data much more rapidly than a processor can transfer data to the FIFO buffer. Consequently, a FIFO buffer may be able to handle much more data than indicated by the value of empty space in the FIFO buffer.
It is desirable to be able to handle data available at the FIFO buffer without slowing the operation of the computer by constantly reading a value in a flow control register yet still be able to handle situations in which data is being processed slowly through the FIFO buffers.